5301ELE Digital System Evaluation Coursework, Level 5, LJMU 2024

Coursework Title: Digital System Evaluation

Module Name: Digital and Embedded System
Module Code: 5301ELE AND 5401ELE
Level: 5
Credit Rating: 20
Weighting: 15%
Lecturers: Dr Princy Johnson
Mieke Sooi
Contact: If you have any issues with this coursework, you may contact your lecturer.
Contact details are:
Email: r.m.sooi@ljmu.ac.uk
Tel: 01512315354
Room: 5.19b (James Parson Building, Byrom Street)
Email: p.johnson@ljmu.ac.uk
Tel: 01512312588
Room: 5.18a (James Parson Building, Byrom Street)
Issue Date: 10.10.2024
Hand-in Date: 31.10.24 (demonstration and viva)
08.11.24 (portfolio submission)
Hand-in Method: lab demo and portfolio submission via Canvas
Feedback Date: within 3 working weeks of portfolio submission
Feedback Method: via Canvas and face-to-face
Programme: BEng Electrical and Electronics Engineering

Learning outcome(s):                                                                                                                    LO1 Define electronic circuit operations and design.
LO2 Design, analyse and implement finite state machine based digital circuits.

Instructions:                                                                                                                                           This coursework requires you to design, implement and evaluate a digital system by applying the knowledge you have gained through the lecture and lab sessions on this topic.

Coursework description                                                                                                                 Lab demonstration: 

Build a combinational logic circuit, using one of the 3 ways developed in the second digital lab, to implement the following function.                                                                                       ????(????, ????, ????) = ????1 + ????3 + ????6
                                    ????(????, ????, ????) = ∑????(1,3,6)                                                                                     
Connect the lower three bits of the divide by 16 counter   (asynchronous/ripple) counter using JK flip flops to one of the circuits’ inputs and collect evidence of correct operation for your report.
Increase the clock frequency to demonstrate correct operation at a high frequency.
Carry out the above steps using Logisim environment before moving onto hardware implementation.

 Portfolio submission: In addition to providing evidence of the correct operation of your circuits, you should also compare different circuit designs in terms of (i) propagation delay, (ii) cost of components and (iii) size of components (approx. transistor count). 

You may want to consider the class notes, lab sheets and the references given in the reading list for this module. 

Assessment deadlines                                                                                                                 Please note there two submission deadlines to this coursework. The hardware implementation should be demonstrated during the lab session on 31 st October 2024. In addition, a final written report should be submitted before midnight on 8th November 2024. You could start submitting the work anytime from two weeks after the coursework is issued.

 Assessment mark and feedback                                                                                                This assessment will constitute 15% of the module mark. The summative feedback on the assessment will be provided through Canvas, and a face-to-face feedback will be given if requested.

Marking Scheme for the assessment

Recommended reading.

1. Title Fundamental of Logic Design
Published 2013
Author C. H. Roth Jr and L.L. Kinney
7th edition ‘International Ed

2. Title: Introduction to Digital design
Author Ercegovac, M, Lang, T, Moreno, JH,
ISBN 9780471527992

3. Title: Digital Design
Author M. Morris Mano
ISBN 9780132774208

Personal Circumstances                                                                                                                The University acknowledges that there may be occasions when a student’s performance in assessment may be adversely affected by serious and exceptional factors outside their control. Such events include sudden acute illness or close personal bereavement.
The Personal Circumstances procedure operates within specific deadlines   following the affected assessment event.

For information about the Personal Circumstances process please visit:
https://policies.ljmu.ac.uk/UserHome/Policies/PolicyDisplay.aspx?&id=254&l=1

Coursework, which is submitted up to 5 working days late (except where there is an agreed extension) will be capped at the pass mark for the module. Coursework submitted after this period (except where there is an agreed extension) will be recorded as a non submission.
This applies to the first submission attempt only at the module. Late submissions at all referral attempts will be recorded as a non-submission.

To request a ‘Personal Circumstances – Extension’ (not possible for examinations) or to make an application for ‘Personal Circumstances – Missed Assessment’ access the Registry Services portal– by selecting ‘Personal Circumstances’ via My LJMU/My Services: https://myservices.ljmu.ac.uk/

Academic Misconduct
The Faculty takes Academic Misconduct very seriously and any suspected cases will be investigated in line with the regulations:  https://www.ljmu.ac.uk/about-us/public-information/studentregulations/academic-misconduct

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